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asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 1 - general description the ak4357 is six channels 24bit dac corresponding to digital audio system. using akm's advanced multi bit architecture for its modulator the ak4357 delivers a wide dynamic range while preserving linear ity for improved thd+n performance. the ak4357 has full differential scf output s, removing the need for ac coupling capacitors and increasing performance for systems with excessive clock jitter. the ak4357 accepts 192khz pcm data and 1 - bit dsd data, ideal for a wide range of applications including dvd - audio and sacd. f eatures o sampling rate ranging from 8khz to 192khz o 24bit 8 times digital filter with slow roll - off option o thd+n: - 90db o dr, s/n: 106db o high tolerance to clock jitter o low distort ion differential output o dsd data input available o channel independent digital de - emphasis for 32, 44.1 & 48khz sampling o zero detect function o channel independent digital attenuator with soft - transition ( 3 speed mode) o soft mute o 3 - wire serial inter face for volume control o master clock: 256fs, 384fs, 512fs or 768fs (pcm normal speed mode) 128fs, 192fs, 256fs or 384fs (pcm double speed mode) 128fs or 192fs (pcm quad speed mode) 512fs or 768fs (dsd mode) o power supply: 4.75 to 5.25v o 48pin lqfp pack age scf dac datt dzf lout1+ lout1- scf dac datt rout1+ rout1- scf dac datt lout2+ lout2- scf dac datt rout2+ rout2- scf dac datt lout3+ lout3- scf dac datt rout3+ rout3- audio i/f control register ak4357 mclk lrck bick dclk dsdl1 dsdr1 csn cclk cdti sdti1 sdti2 sdti3 dsdl2 dsdr2 dsdl3 dsdr3 pcm dsd 192khz 24 - bit 6ch dac with dsd input ak43 57
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 2 - n ordering guide AK4357VQ - 40 ~ +85 c 48lqfp akd4357 evaluation board for ak4357 n pin layout lout1- rout1+ 1 lout1+ 48 2 dzfl1 3 dafr1 4 dzf23 5 cad0 6 cad1 7 pdn 8 bick 9 mclk 10 dvdd rout1- 47 lout2+ 46 45 44 rout2- 43 lout3+ 42 lout3- 41 rout3+ 40 rout3- 39 avss 38 dvss 13 sdti1 14 sdti2 15 sdti3 16 lrck 17 18 cclk 19 cdti 20 csn 21 dsdm 22 dclk 23 36 35 34 33 32 31 30 29 28 27 26 avss avdd vrefh dif2 dif1 dif0 dsdr3 dsdl3 dsdr2 dsdl2 dsdr1 AK4357VQ top view smute lout2- rout2+ avss 37 nc 24 11 nc 12 25 dsdl1 pin/function no. pin name i/o function 1 lout1 - o dac1 lch negative analog output pin 2 lout1+ o dac1 lch positive analog output pin 3 dzfl1 o dac1 lch zero input detect pin 4 dzfr1 o dac1 rch zero input detect pin 5 dzf23 o dac2,3 zero input detect pin 6 cad0 i chip address 0 pin 7 cad1 i chip address 1 pin 8 pdn i power - down mode pin when at ? l ? , the ak4357 is in the power - down mode and is held in reset. the ak4357 should always be reset upon power - up. 9 bick i audio serial data clock pin 10 mclk i master clock input pin an external ttl clock should be input on this pin.
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 3 - no. pin name i/o function 11 dvdd - digital power supply pin, +4.75 ~ +5.25v 12 nc - nc pin no internal bonding 13 dvss - digital ground pin 14 sdti1 i dac1 audio serial data input pin 15 sdti2 i dac2 audio serial data input p in 16 sdti3 i dac3 audio serial data input pin 17 lrck i l/r clock pin 18 smute i soft mute pin when this pin goes to ? h ? , soft mute cycle is initialized. when returning to ? l ? , the output mute releases. 19 cclk i control data clock pin 20 cdti i control data input pin 21 csn i chip select pin 22 dsdm i dsd mode enable pin (pull - down pin) ? 0 ? : pcm mode ? 1 ? : dsd mode 23 dclk i dsd clock pin 24 nc - nc pin no internal bonding 25 dsdl1 i d ac1 dsd lch data input pin 26 dsdr1 i dac1 dsd rch data input pin 27 dsdl2 i dac2 dsd lch data input pin 28 dsdr2 i dac2 dsd rch data input pin 29 dsdl3 i dac3 dsd lch data input pin 30 dsdr3 i dac3 dsd rch data input pin 31 dif0 i audio data interfa ce format 0 pin 32 dif1 i audio data interface format 1 pin 33 dif2 i audio data interface format 2 pin 34 vrefh i positive voltage reference input pin 35 avdd - analog power supply pin, +4.75 ~ +5.25v 36 avss - analog ground pin 37 avss - analog gr ound pin 38 avss - analog ground pin 39 rout3 - o dac3 rch negative analog output pin 40 rout3+ o dac3 rch positive analog output pin 41 lout3 - o dac3 lch negative analog output pin 42 lout3+ o dac3 lch positive analog output pin 43 rout2 - o dac2 rch negative analog output pin 44 rout2+ o dac2 rch positive analog output pin 45 lout2 - o dac2 lch negative analog output pin 46 lout2+ o dac2 lch positive analog output pin 47 rout1 - o dac1 rch negative analog output pin 48 rout1+ o dac1 rch positive an alog output pin note: all input pins except pull - down pin should not be left floating.
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 4 - a bsolute maximum ratings (avss, dvss =0v ; note 1) parameter symbol min max units power supplies analog digital |avss - dvss| (note 2) a vdd d vd d d gnd - 0.3 - 0.3 - 6.0 6.0 0.3 v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina - 0.3 a vdd +0.3 v digital input voltage vind - 0.3 d v d d+0.3 v ambient operating temperature ta - 4 0 85 c storage temperature tstg - 65 150 c note : 1 . all voltages with respect to ground . 2. avss and dvss must be connected to the same analog ground plane . warning : operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaran teed at these extremes. recommended operating conditions (avss, dvss =0v ; note 1) parameter symbol min typ max units power supplies (note 3) analog d igital a v dd dvdd 4.75 4.75 5.0 5.0 5.25 5.25 v v voltage reference vref avdd - 0.5 - avdd v note: 1. all voltages with respect to ground. 3. the power up sequence between avdd and dvdd is not critical. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 5 - analog characteristics ( ta=25 c ; avdd , dvdd = 5 v ; vref =avdd ; fs=4 4.1k hz ; bick=64fs; signal frequency=1khz ; 24bit input data; measurement frequency=20hz ~ 20khz; r l 3 4k w ; unless otherwise specified ) parameter min typ max units resolution 24 bits dynamic characteristics (note 4) fs=44.1khz bw=20khz 0dbfs - 90 - 86 db fs=96khz bw=40khz 0dbfs - 88 - 84 - db db thd +n fs=192khz bw=40khz 0dbfs - 86 - - db db dynamic range ( - 60dbfs with a - weighted) (note 5) 100 106 db s/n (a - we ighted) (note 6) 100 106 db interchannel isolation (1khz) 90 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy gain drift 100 - ppm/ c output voltage (note 7) 2.35 2.5 2.65 vpp load resistance (note 8) 4 k w power supplies power supply current (avdd+dvdd) normal operation (pdn = ? h ? , fs 96khz ) normal operation (pdn = ? h ? , fs=192khz ) power - d own mode (pdn = ? l ? ) (note 9) 50 60 10 75 85 100 ma ma a note: 4. measured by audio precision system two. refer to the evaluation board manual. 5. 100db at 16bit data. 6. s/n is independent of input bit length. 7. fu ll scale voltage (0db). output voltage scales with the voltage of vrefh pin. aout(typ.@0db)=(aout+) - (aout - )= 2.5vpp*vrefh/5.0 8. for ac - load. 8 k w for dc - load 9. all digital inputs including clock pins (mclk, bick and lrck) are held dvdd or dvss.
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 6 - sharp roll - off filter characteristics ( ta = 25 c ; avdd, dvdd = 4.75 ~ 5.25 v ; fs = 4 4.1k hz ; dem = off; slow= ? 0 ? ; pcm mode) parameter symbol min typ max units digital filter passband 0.05db (note 9) - 6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 10) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay (note 11) gd - 19.1 - 1/fs digital filter + scf fr equency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.2 0.3 +0/ - 0.6 - - - db db db note s: 10. the passband and stopband frequencies scale with fs(system sampling rate). for example, pb=0.4535 fs (@ 0.05db), sb=0.54 6 fs. 11. the calculating delay time which occurred by digital filtering. this time is from setting the 16/24bit data of both channels to input register to the output of analog signal. slow roll - off f ilter characteristics (ta = 25 c ; avdd , dvdd = 4.75~5.25v; fs = 44.1 khz; dem = off; slow = ? 1 ? ; pcm mode ) parameter symbol min typ max units digital filter passband 0.04db (note 12) - 3.0db pb 0 - 18.2 8.1 - khz khz stopband (note 12) sb 39.2 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay (note 11) gd - 19.1 - 1/fs digital filter + scf frequency response 20.0khz 40.0 khz 80.0khz fs=44.khz fs=96khz fs=192khz fr fr fr - - - +0/ - 5 +0/ - 4 +0/ - 5 - - - db db db note: 12 . the passband and stopband frequencies scale with fs. for example, pb = 0. 185 fs (@ 0.0 4 db), sb = 0. 888 fs. dc characteristics ( ta = 25 c ; avdd, dvdd = 4.75 ~ 5.25 v ) parameter symbol min typ max units high - level input voltage low - level input voltage vih vil 2.2 - - - - 0.8 v v high - level output voltage (iout = - 80 a) low - level output voltage (iout = 80 a) voh vol dvdd - 0.4 - - - 0.4 v v input leakage current (note 13) iin - - 10 a note: 13 . dsdm pin has internal pull - down devices, nominally 100k w .
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 7 - switching characteristics ( ta = 25 c ; avdd, dvdd = 4.75 ~ 5.25 v ; c l = 20pf) parameter symbol min typ max uni ts master clock frequency duty cycle fclk dclk 2.048 40 11.2896 36.864 60 mhz % lrck frequency normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 60 120 45 48 96 192 55 khz khz khz % pcm audio interface timing bick period normal speed mode double/quad speed mode bick pulse width low pulse width high bick ? - ? to lrck edge (note 13) lrck edge to bick ? - ? (note 13) sdti hold time sdti setup time tbck tbck tbckl tbckh tblr tl rb tsdh tsds 1/128fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns dsd audio interface timing dclk period dclk pulse width low pulse width high dclk edge to dsdl/r (note 14) tdck tdckl tdckh tddd 1/64fs 160 160 - 20 20 ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn high time csn ? ? to cclk ? - ? cclk ? - ? to csn ? - ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns reset timing pdn pulse width (note 15) tpd 150 ns no te s: 13. bick rising edge must not occur at the same time as lrck edge. 14. dsd data transmitting device must meet this time. 15. the ak4357 can be reset by bringing pdn = ? l ? .
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 8 - n timing diagram 1/fclk tclkl vih tclkh mclk vil dclk =tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr audio serial interface timing (pcm mode) vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck audio serial interface timing (dsd normal mode, dckb = ? 0 ? )
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 9 - vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck tddd audio seri al interface timing (dsd phase modulation mode, dckb = ? 0 ? ) tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing tpd vil pdn power - down timing
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 10 - operation overview n d/a conversion m ode the ak4357 can perform d/a conversion for both pcm data and dsd data. when dsd mode, dsd data can be input from dclk, dsdl1 - 3 and dsdr1 - 3 pins. when pcm mode, pcm data can be input from bick, sdti1 - 3 and lrck pins. pcm/dsd mode change s by dsdm pin or d/p bit , dsdm pin setting and d/p bit setting are ored internal. when pcm/dsd mode change s by dsdm pin or d/p bit , the ak43 57 should be reset by rstn bit , pw bit (pw1=pw2=pd3= ? 0 ? ) or pdn pin . it takes about 2/fs to 3/fs to change the mode. dsdm pin d/p bi t dac output 0 pcm l 1 dsd 0 dsd h 1 dsd table 1 . dsd/pcm mode control n system clock 1) pcm mode the external clocks, which are required to operate the ak43 57 , are mclk, lrck and bick. the master clock (mclk) should be synchronized with lrck bu t the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two methods to set mclk frequency. in manual setting mode (acks = ? 0 ? : register 00h), the sampling speed is set by dfs0/1(tab le 2). t he frequency of mclk at each sampling speed is set automatically. (table 3 ~ 5 ). in auto setting mode (acks = ? 1 ? : default), as mclk frequency is detected automatically (table 6), and the internal master clock becomes the appropriate frequency (table 7), it is not necessary to set dfs0/1. all external clocks (mclk , bick and lrck) should always be present whenever the ak4357 is in the normal operation mode ( pdn= ? h ? ). if these clocks are not provided, the ak4357 may draw excess current and may fall into unpredictable operation. this is because the dev ice utilizes dynamic refreshed logic internally. the ak4357 should be reset by pdn= ? l ? after threse clocks are provided. if the external clocks are not present, the ak4357 should be in the power - down mode (pdn= ? l ? ). after exiting reset( pdn = ? - ? ) at powe r - up etc., the ak4357 is in the power - down mode until mclk is input. dsd interface signals (dclk, dsdl1 - 3, dsdr1 - 3) are fixed to ? h ? or ? l ? . dfs1 dfs0 sampling rate (fs) 0 0 normal speed mode 8khz ~ 48khz default 0 1 double speed mode 60khz ~ 96khz 1 0 qua d speed mode 120khz ~ 192khz table 2. sampling speed (manual setting mode) lrck mclk bick fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920mhz 12.2880mhz 16.3840mhz 24.5760mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 2.8224mhz 48 .0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 3.0720mhz table 3. system clock example (normal speed mode @manual setting mode)
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 11 - lrck mclk bick fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 5.6448mhz 96.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 6.1440mhz table 4. system clock example (double speed mode @manual setting mode) lrck mclk bick fs 128fs 192fs 64fs 176.4khz 22.5792mhz 33.8688mhz 11.2896mhz 192.0khz 24.5760mhz 36.8640mhz 12.2880mhz ta ble 5. system clock example (quad speed mode @manual setting mode) mclk sampling speed 512fs 768fs normal 256fs 384fs double 128fs 192fs quad table 6. sampling speed (auto setting mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 51 2fs 768fs sampling speed 32.0khz - - - - 16.3840 24.5760 44.1khz - - - - 22.5792 33.8688 48.0khz - - - - 24.5760 36.8640 normal 88.2khz - - 22.5792 33.8688 - - 96.0khz - - 24.5760 36.8640 - - double 176.4khz 22.5792 33.8688 - - - - 192.0khz 24.5760 36.864 0 - - - - quad table 7. system clock example (auto setting mode) 2) dsd mode the external clocks, which are required to operate the ak43 57 , are mclk and dclk . the master clock (mclk) should be synchronized with dsd clock (dclk) but the phase is not critic al . the frequency of mclk is set by dcks bit. all external clocks (mclk , dclk) should always be present whenever the ak4357 is in the normal operation mode ( pdn= ? h ? ). if these clocks are not provided, the ak4357 may draw excess current because the device utilizes dynamic refreshed logic internally. the ak4357 should be reset by pdn= ? l ? after threse clocks are provided. if the external clocks are not present, the ak4357 should be in the power - down mode (pdn= ? l ? ). after exiting reset( pdn = ? - ? ) at power - u p etc., the ak4357 is in the power - down mode until mclk is input. pcm interface signals (bick, lrck, sdti1 - 3) are fixed to ? h ? or ? l ? . dcks 0 1 mclk 512fs 768fs dclk 64fs 64fs table 8. system clock (fs=44.1khz)
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 12 - n audio serial interface format 1) pcm mode when pcm mode, data is shifted in via the sdti1 - 3 pins using bick and lrck inputs. the dif0 - 2 as shown in table 7 can select five serial data modes . initial value of dif0 - 2 bits is ? 000 ? , each dif0 - 2 bits is ored with dif0 - 2 pins. in all modes the serial data is msb - first, 2 ? s compliment format and is latched on the rising edge of bick. mode 2 can be used for 16/20 msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 sdti format bick figure 0 0 0 0 16bit lsb justified 3 32fs figure 1 1 0 0 1 20bit lsb justified 3 40fs figure 2 2 0 1 0 24bit msb justified 3 48fs figure 3 3 0 1 1 24bit i 2 s compatible 3 48fs figure 4 4 1 0 0 24bit lsb justified 3 48fs figure 2 table 9. audio data formats sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 (32fs) (64fs) 0 14 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don ? t care don ? t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 1. mode 0 timing sdti lrck bick (64fs) 0 9 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don ? t care don ? t care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don ? t care don ? t care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1,4 timing
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 13 - lrck bick (64fs) sdti 0 22 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don ? t care 23 lch data rch data 23 30 22 2 24 23 30 22 1 0 don ? t care 23 22 23 figure 3. mode 2 timing lrck bick (64fs) sdti 0 3 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don ? t care 23 lch data rch data 23 25 3 2 24 23 25 22 1 0 don ? t care 23 23 figure 4. mode 3 timing 2) dsd mode in case of dsd mode, dif0 - 2 are ignored. the frequency of dclk is fixed to 64fs. dckb bit can invert the polarity of dclk. dclk (64fs) dckb=1 dclk (64fs) dckb=0 dsdl,dsdr normal dsdl,dsdr phase modulation d1 d0 d1 d2 d0 d2 d3 d1 d2 d3 figure 5. dsd mode timing
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 14 - n de - emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is enabled or di sabled with dem0 and dem1. in case of double speed and quad speed mode, the digital de-emphasis filter is always off. when dsd mode, dem0 - 1 is invalid. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 8 . de-emphasis f ilter c ontr ol ( normal speed mode) n output volume the ak4357 includes channel independent digital output volumes (att) with 128 levels at 0.5db steps including mute. these volumes are in front of the dac and can attenuate the input data from 0db to ? 63db and mute. transition time is set by ast1 - 0 bits(table12) when changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. att7 - 0 attenuation level ffh 0db feh - 0.5db fdh - 1.0db : : 82h - 62.5db 81h - 63.0db 80h mute ( - ) : : 02h mute ( - ) 01h mute ( - ) 00h mute ( - ) default table 11. attenuation level of output volume mode ats1 ats0 att speed 0 0 0 1792/fs 1 0 1 896/fs 2 1 0 256/fs 3 1 1 256/fs default table 12. transition time of output volume in case mode0, it takes 1792/ fs to transit from ffh(0db) to 80 h( mute). in case mode1, it takes 896/ fs to transit from ffh(0db) to 80 h( mute). in case mode2 and 3,it takes 256/ fs to transit from ffh(0db) to 80 h ( mute). i f pdn pin goes to ? l ?, att 7 - 0 registers are initialized to ffh.attn7 - 0 registers go to ffh when rstn bit is set to ? 0 ? . when rstn bit returns to ? 1 ? , att7 - 0 registers go to the set value. digital output volume function is independent of soft mute function. the setting value of the register is held when switching between pcm mode and dsd mode.
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 15 - n zero d etection when the input data at all channels are continuously zero s for 8192 lrck cycles, the ak4357 has zero detection like table 13. dzf pin immediatel y goes to ? l ? if input data of each channel is not zero after going dzf ? h ?. if rstn bit is ? 0 ?, dzf pin go es to ? h ?. dzf pin go es to ? l ? at 4 ~ 5lrck if input data of each channel is not zero after rstn bit returns to ? 1 ?. zero detect function can be disabl ed by dzfe bit. in this case, dzf pins of both channels are always ? l ?. dzfb bit can invert the polarity of dzf pin. when one of pw1 - 3 bit is set to ? 0 ? , the input data of dac which the pw bit is set to ? 0 ? should be zero in order to enable zero detection of the other channels . when all pw1 - 3 bits are set to ? 0 ? , dzf pin fixes ? l ? . when dzfm bit set to ? 1 ? , only the input data at all channels are continuously zero s for 8192 lrck cycles , all dzf pins go to ? h ? . dzf pin operations dzfl1 when lch data of dac1 is ? 0 ? , dzfl1 pin goes ? h ? . dzfr1 when rch data of dac1 is ? 0 ? , dzfr1 pin goes ? h ? . dzf23 when all lch and rch data of dac2,3 are ? 0 ? , dzf23 goes ? h ? . table 13. dzf pin operations n soft mute operation soft mute operation is performed at digital do main. when the smute bit goes to ? 1 ? , the output signal is attenuated by - during att_data att transition time (table 12) from the current att level. when the smute bit is returned to ? 0 ? , the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit attenuation dzf pin att level - aout 8192/fs gd gd (1) (2) (3) (4) (1) notes: (1) att_data att transition time (table 12). for example, in normal speed mode, this time is 1792lrck cycles (1792/fs) at att_data=128. (2) the analog output c orresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at each channel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to ? h ? . dzf pin immediately goes to ? l ? if input data are not zero after going dzf ? h ? . figure 6. soft mute and zero detection
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 16 - n system reset the ak4357 should be res et once by bringing pdn = ? l ? upon power - up. the analog section exits power - down mode by mclk input and then the digital section exits power - down mode after the internal counter counts mclk during 4/fs. n power - down the ak4357 is placed in the power - down mode by bringing pdn pin ? l ? and the anlog outputs are floating (hi - z). figure 6 shows an example of the system timing at the power - down and power - up. each dac can be powered down by each power - down bit (pw1 - 3) ? 0 ? . in this case, the internal register val ues are not initialized and the analog output is hi - z. because some click noise occurs, the analog output should be muted externally if the click noise influences system application. normal operation internal state pdn power-down n ormal operation gd gd ? 0 ? data d/a out (analog) d/a in (digital) clock in mclk, lrck, bick (1) (3) (6) dzf external mute (5) (3) (1) mute on (2) (4) don ? t care notes: ( 1) the a nalog output correspondin g to digital input ha s the group delay (gd). (2) analog outputs are floating (hi -z) at the power-down mode. (3) click noise occurs at the edge of pdn signal . this noise is output even if ? 0 ? data is input. (4) t he external clocks (mclk, bick and lrck) c an be stopped in the power-down mode (pdn = ? l ? ) . (5) please mute the analog output externally if the click noise ( 3 ) influence system application. the timing example is shown in this figure. (6) dzf pins are ? l ? in the power - down mode (pdn = ? l ? ). figur e 7 . power-down/up se quence e xample
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 17 - n reset function when rstn =0, dac is powered down but the internal register values are not initialized. the analog outputs go to vcom voltage and dzf l/dzfr pin s go to ?h?. figure 8 shows the example of reset by rstn bi t. internal state rstn bit digital block power-down normal operation gd gd ? 0 ? data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) dzf (3) (1) (2) normal operation 2/ fs( 5) internal rstn bit 2~3/fs (6) 3~4/fs (6) don ? t care (4) notes: ( 1) the a nalog output corresponding to digital input ha s the group delay (gd). (2) analog outputs go to vcom voltage . (3) click noise occurs at the edges( ? - ? ) of the internal timing of rstn bit . this noise is out put even if ? 0 ? data is input. (4) t he external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn = ? l ? ) . (5) dzf pins go to ? h ? when the rstn bit becomes ? 0 ?, and go to ? l ? at 2/fs after rstn bit becomes ? 1 ?. (6) there is a delay, 3 ~ 4/fs from rstn bit ?0? to the internal rstn bit ? 0 ? , and 2 ~ 3/fs from rstn bit ? 1 ? to the internal rstn ? 1 ? . figure 8. reset sequence example
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 18 - n d/a conversion mode switching timing rstn bit d/a data d/a mode 3 4/fs 3 0 pcm data dsd data pcm mode dsd mode figure 9 . d/a mode switching timing (pcm to ds d) rstn bit d/a data d/a mode 3 4/fs dsd data pcm data dsd mode pcm mode figure 10 . d/a mode switching mode timing (dsd to pcm) caution: in dsd mode, the signal level is ranging from 25% to 75%. peak levels of dsd signal above this duty are not recommended by sacd format book (scarlet book).
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 19 - n mode control interface internal registers may be written by 3 - wire p interface pins , csn , cclk and cdti. the data on this interface consists of c hip a ddress (2bits, c 1/0 ; fixed to ?01?), read/write (1bit; fixed to ?1? , write only ), register a ddress (m sb first, 5bits) and control d ata (msb first, 8bits). the ak43 57 latches the data on the rising edge of cclk, so data should clocked in on the falling edge. the writing of data becomes valid by csn ? - ?. the clock speed of cclk is 5mhz (max). pdn = ?l? resets the registers to their default values. t he internal timing circuit is reset by rstn bit, but the registers are not initialized. cdti cclk csn c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1 - c0: chip addr ess (c1=cad1, c0=cad0) r/w: read/write (fixed to ? 1 ? , write only) a4 - a0: register address d7 - d0: control data figure 11 . control i/f timing *the ak43 57 does not support the read command and chip address. *when the ak4357 is in the power down mode (pdn = ? l ? ) or the mclk is not provided, writing into the control register is inhibited . n register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks slow dzfm dzfe dif2 dif1 dif0 rstn 01h control 2 0 0 0 0 0 0 smute rstn 02h speed & power down control 0 0 dfs1 dfs0 pw3 pw2 pw1 rstn 03h de - emphasis control 0 0 0 0 0 0 dem1 dem0 04h lout1 att control att7 att6 att5 att4 att3 att2 att1 att0 05h rout1 att control att7 att6 att5 att4 att3 att2 att1 att0 06h lout2 att control att7 att6 att5 att4 att3 att2 att1 att0 07h rout2 att control att7 att6 att5 att4 att3 att2 att1 att0 08h lout3 att control att7 att6 att5 att4 att3 att2 att1 att0 09h rout3 att control att7 att6 att5 att4 att3 att2 att1 att0 0ah control 3 0 0 dcks d/p dckb dzfb ats1 ats0 note: for addresses from 0bh to 1fh, data must not be written. when pdn goes to ? l ? , the registers are initialized to their default values. when rstn bit goes to ? 0 ? , the only internal timing is reset, and the registers are not initialized to th eir default values. all data can be written to the registers even if pw1 - 3 or rstn bit is ? 0 ? .
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 20 - n register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks slow dzfm dzfe dif2 dif1 dif0 rstn default 1 0 0 1 0 0 0 1 rstn : in ternal timing reset 0: reset. all dzf pins go to ? h ? and any registers are not initialized. 1: normal operation when mclk frequency or dfs change s , the ak43 57 should be reset by pdn pin or rstn bit. dif2 - 0: audio data interface modes (see table 9, pcm only) initial: ? 000 ? , mode 0 register bits of dif2 - 0 are ored with the dif2 - 0 pins. dzfe: data zero detect enable 0: disable 1: enable zero detect function can be disabled by dzfe bit ? 0 ? . in this case, the dzf pins are always ? l ? . dzfm: data zero detect mode 0: channel separated mode (see table 13.) 1: channel anded mode if the dzfm bit is set to ? 1 ? , all dzf pins go to ? h ? only when the input data at all channels are continuously zeros for 8192 lrck cycl es. slow: slow roll - off filter enable (pcm only) 0: sharp roll - off filter 1: slow roll - off filter acks : master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequenc y is detected automatically at acks bit ? 1 ?. in this case, the setting of dfs1 - 0 are ignored. when this bit is ? 0 ? , dfs1 - 0 set the sampling speed mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 0 0 0 0 smute rstn default 0 0 0 0 0 0 0 1 rstn : internal timing reset 0: reset. all dzf pins of go to ? h ? and any registers are not initialized. 1: normal operation when mclk frequency or dfs change s , the ak43 57 should be reset by pdn pin or rstn bit. smute: soft mute enable 0: normal operation 1: all dac outputs soft - muted
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 21 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h speed & power down control 0 0 dfs1 dfs0 pw3 pw2 pw1 rstn default 0 0 0 0 1 1 1 1 rstn : internal timing reset 0: reset. all dzf pins go to ? h ? and any registers are not initialized. 1: normal operation when mclk frequency or dfs change s , the ak43 57 should be reset by pdn pin or rstn bit. pw3 - 1: power - down control (0: power - down, 1: power - up) pw1: power down control of da c1 pw2: power down control of dac2 pw3: power down control of dac3 all sections are powered - down by pw1=pw2=pw3=0. dfs1 - 0:sampling speed control (see table 2, pcm only) 00: normal speed 01: double speed 10: quad speed when changing between normal/double speed mode and quad speed mode, some click noise occurs. addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h de - emphasis control 0 0 0 0 0 0 dem1 dem0 default 0 0 0 0 0 0 0 1 dem1 - 0: de - emphasis response contro l for dac1/2/3 data on sdti1/2/3/ (see table 10, pcm only) initial: ? 01 ?, off
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 22 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h lout1 att control att7 att6 att5 att4 att3 att2 att1 att0 05h rout1 att control att7 att6 att5 att4 att3 att2 att1 att0 06h lout2 att control att7 att6 att5 att4 att3 att2 att1 att0 07h rout2 att control att7 att6 att5 att4 att3 att2 att1 att0 08h lout3 att control att7 att6 att5 att4 att3 att2 att1 att0 09h rout3 att control att7 att6 att5 att4 att3 att2 att1 att0 defa ult 1 1 1 1 1 1 1 1 att7 - 0: attenuation level 128 levels, 0.5db step (see table 11) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah control 3 0 0 dcks d/p dckb dzfb ats1 ats0 default 0 0 0 0 0 0 0 0 ats1 - 0: datt speed setting (see table 12) initial: ? 00 ? , mode 0 dzfb : inverting enable of dzf 0: dzf goes ? h ? at zero detection 1: dzf goes ? l ? at zero detection dckb : polarity of dclk (dsd only) 0: dsd data is output from dclk falling edge 1: dsd data is output from dclk rising edge d/p : dsd/pcm mode select 0: pcm mode. sclk, sdti1 - 3, lrck 1: dsd mode. dclk, dsdl1 - 3, dsdr1 - 3 d/p bit is ored with the dsdm pin. when d/p change s , the ak43 57 should be reset by pdn pin , pw bit or rstn bit. dcks : master clock frequency select at dsd mode (dsd only) 0: 512fs 1: 768fs
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 23 - system design figure 12 shows the system connection diagram. an evaluation board (akd4357) is available in order to allow an easy study on the layout of a surrounding circuit. ak4357 top view clock gen dsp up + mode lpf lpf lpf lpf lpf lpf mute l1ch out mute r1ch out mute l2ch out mute r2ch out mute l3ch out mute r3ch out + analog 5v digital 5v system ground analog ground reset 10u 0.1u 0.1u 10u dvdd 11 mclk 10 bick 9 pdn 8 cad1 7 cad0 6 dzf23 5 dzfr1 4 dzfl1 3 lout1+ 2 lout1- 1 nc 12 dsdl1 25 dsdr1 26 dsdl2 27 dsdr2 28 dsdl3 29 dsdr3 30 dif0 31 dif1 32 dif2 33 vrefh 34 avdd 35 avss 36 dvss 13 sdti1 14 sdti2 15 sdti3 16 lrck 17 smute 18 cclk 19 cdti 20 csn 21 dsdm 22 dclk 23 nc 24 48 47 46 45 44 43 42 41 40 39 38 rout1+ rout1- lout2+ lout2- rout2+ rout2- lout3+ lout3- rout3+ rout3- avss 37 avss control dsd data cont- roller figure 12. ty pical connection diagram notes: - lrck = fs, bick = 64fs. - when aout drives some capacitive load, some resistor should be added in series between aout and capacitive load. - all input pins except pull-down pins should not be left floating.
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 24 - analog ground digital ground system controller dvss dvdd 13 sdti1 11 14 sdti2 15 sdti3 16 lrck 17 smute 18 cclk 19 cdti 20 csn 21 dsdm 22 dclk 23 dsdl1 25 48 rout1+ ak4357 26 27 28 29 30 31 32 33 34 35 dsdr1 dsdl2 dsdr2 dsdl3 dsdr3 dif0 dif1 dif2 vrefh avdd 47 rout1- 46 lout2+ 45 lout2- 44 rout2+ 43 rout2- 42 lout3+ 41 lout3- 40 rout3+ 39 rout3- 38 avss mclk 10 bick 9 pdn 8 cad1 7 cad0 6 dzf23 5 dzfr1 4 dzfl1 3 lout1+ 2 lout1- 1 nc 12 nc 24 36 avss 37 avss figure 13. ground layout 1. grounding and power supply decoupling avdd and dvdd are usually supplied from analog supply in system and should be separated from system digital supply. alternatively if avdd and dvdd are supplied sepa rately, the power up sequence is not critical. avss and dvss of the ak4357 must be connected to analog ground plane . system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitor, especially 0.1 m f ceramic capacitor for high frequency should be placed as near to avdd and dvdd as possible. 2. voltage r eference vrefh sets the analog output range. vrefh pin is normally connected to avdd with a 0.1 m f ceramic cap acitor. all signals, especially clocks, should be kept away from the vrefh pin in order to avoid unwanted coupling into the ak4357. 3. analog outputs the analog outputs are full - differential outputs and 0.5 x vrefh vpp (typ) centered around the internal common voltage (about avdd/2). the differential outputs are summed externally, v aout =(aout+) - (aout - ) between aout+ and aout - . if the summing gain is 1, the output range is 5.0vpp (typ @vrefh=5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2 ? s complement. the output voltage(v aout ) is a positive full scale for 7fffff (@24bit) and a negative full scale for 800000h (@24bit). the ideal v aout is 0v for 000000h (@24bit). the internal switched - capacitor filte r and external low pass filter attenuate the noise generated by the delta - sigma modulator beyond the audio passband. dc offset on aout+/ - is eliminated without ac coupling since the analog outputs are differential.
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 25 - 4. external analog filter it is recom mended by sacd format book (scarlet book) that the filter response at sacd playback is an analog low pass filter with a cut - off frequency of maximum 50khz and a slop of minimum 30db/oct. the ak4357 can achieve this filter response by combination of the int ernal filter (table 14) and an external filter (figure 14). frequency gain 20khz - 0.4db 50khz - 2.8db 100khz - 15.5db table 14. internal filter response at dsd mode 1.8k 4.3k 1.0k 1.8k 1.0k 4.3k 270p + vop 270p - vop aout- aout+ 3300p analog out 2.0k 2.0k 47u 47u 2200p - + 2.5vpp 5.65vpp 2.5vpp figure 14. external 3rd order lpf circuit example freque ncy gain 20khz - 0.05dbr 50khz - 0.51dbr 100khz - 16.8dbr dc gain = 1.07db table 15. 3rd order lpf (figure 1 4 ) response
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 26 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0. 08 48pin lqfp(unit:mm) 0.10 37 24 25 36 0.145 0. 05 1.40 0.05 0.13 0. 13 1.70max 0 ~ 10 0.10 m 0.5 0. 2 0.5 n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ ak 4357 ] ms0088 - e - 02 2002 / 0 7 - 27 - marking AK4357VQ xxxxxxx japan 1 akm 1) asahi kasei logo 2) marking code: AK4357VQ 3) date code: xxxxxxx( 7 digits) 4) country of origin 5) pin #1 indication i m portant notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license o r other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one d esigned or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant in jury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing i t, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that pa rty in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notific ation.

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